1. Field of the Invention
The present invention relates to a non-volatile memory circuit and, more particularly, to a non-volatile memory circuit capable of shortening the erasure time for a flash memory which uses memory cells having floating gates.
2. Related Art
A flash memory or non-volatile memory which uses memory cells having floating gates can retain recorded information even when it is powered off and has a faster reading speed than a hard disk or the like. In programming (or writing) memory cells having floating gates, for example, charges are injected into the floating gates to raise the threshold voltages of cell transistors, thereby recording data "0". In an erasing operation, charges are drawn out of the floating gates to reduce the threshold voltage of cell transistors, causing data "1" to be recorded.
The injection and drawing of charges into and out of the floating gates needs a specific time so that changing data takes time if such charge injection and drawing are performed cell by cell. To cope with this shortcoming, in program mode, the conventional memory circuits temporarily render all the memory cells in an erased state which is data "1", then inject charges only to desired or target memory cells to write data "0" there. In the erasing operation, charges are temporarily injected to all the memory cells of data "1" to make all of their threshold voltages in a high state (preprogram) and an erase voltage is simultaneously applied to all the memory cells to render them in a state of data "1" (collective erasure).
As apparent from the above, a flash memory or nonvolatile memory which uses memory cells having floating gates stores given information by changing the state of the target memory cells to data "0" from data "1" in program mode, and preprograms and collectively and simultaneously erase all the memory cells to a state of data "1" in erasing mode.
FIG. 1 is a schematic operational chart of a conventional memory; the horizontal scale represents the number of cells and the vertical scale threshold levels (threshold voltages) and data "1" and "0" of cell transistors. Shown horizontally are (1) erased state (initial state), (2) first writing, (3) first erasing, (4) second writing and (5) second erasing.
The diagram shows a reference voltage (Vref) for writing and erasure. In an ordinary memory circuit, a sense amplifier compares the output voltage corresponding to a cell transistor with the reference voltage. When the threshold voltage of a cell transistor is higher, the cell transistor has a small current value and provides a high output voltage, and when the threshold voltage of the cell transistor is lower, the cell transistor has a large current value and provides a low output voltage. The comparison of the threshold voltage with the reference voltage for the sense amplifier should actually be discussed in connection with the output voltage. As the high/low state of the threshold voltage of each cell transistor corresponds one to one to the high/low state of the output voltage, however, the reference voltage Vref in the cell is used as the reference voltage corresponding to the threshold voltage in the following explanation of this specification. Therefore, changing the setting of the reference voltage in a cell is the same as changing the setting of the reference voltage for the sense amplifier. It is to be noted however that while the high/low states of both reference voltages correspond to each other, their absolute values may differ from each other in some cases.
FIGS. 2A and 2B are diagrams illustrating the transition of data and threshold levels (threshold voltages) of a 4.times.4 memory cell array in accordance with the operations in FIG. 1. FIG. 2A shows the transition of data, and FIG. 2B the transition of the threshold levels of cell transistors. The numerals "0" and "1" in the individual cells in FIG. 2A respectively indicate data "0" and "1", and the numerals "0" and "1" in the individual cells in FIG. 2B respectively indicate a low threshold level Vth1 and a high threshold level Vth2.
In the initial state (1), the threshold levels of all the cell transistors are the low level vth1, so that data of all the cell transistors are "1". In the first writing, charges are injected to the floating gates of the target memory cells to set their threshold levels to the high level Vth2. Accordingly, some of the cells are in the state of the high threshold level Vth2 (data "0"), while the other cells are in the state of the low threshold level Vth1 (data "1").
To implement the second writing (4), erasure is carried out temporarily. That is, in this first erasing (3), those cells which have had the low threshold level Vth1 in the aforementioned state (2) are individually preprogrammed to all have the high threshold level Vth2. Then, the erase voltage is simultaneously applied to all the memory cells to draw the charges from the floating gates, rendering all the cell transistors to have the low threshold level Vth1 (data "1"). In this situation, the second writing (4) is performed to apply a write voltage to target cell transistors to inject charges to their floating gates so that those cell transistors of target memory cells to set their have the high threshold level Vth2 (data "0").
Thereafter, when data rewriting becomes necessary again, the second erasing (5) is executed in the same manner discussed above to render all the cell transistors to have the low threshold level Vth1 (data "1").
The conventional non-volatile memories need to erase all the cell transistors or all the cell transistors in a given sector, every time data is to be rewritten. This erasing operation involves preprogramming and simultaneous erasure and thus takes time. It is undesirable to implement such long and power-consuming erasure every time data is to be rewritten. To rewrite image data in a digital camera, for example, such an erasing operation takes time and suffers increased power consumption.